Back to Clock Domain Crossings (CDC) Report
# CLK_50MHZ (falling) => CLK_50MHZ (rising) |Origin Clock Domain|Target Clock Domain|Number of CDCs|Graph| |---|---|---:|:---:| |CLK_50MHZ (falling)|CLK_50MHZ (rising)|2|| ## CDCs ### Summary |ID|Graph|Origin Signal|Target Signal|Details| |---:|:---:|---|---|:---:| |16||`u2_ddr.data_write2`|`u2_ddr.data_read`|| |18||`u2_ddr.data_write2`|`u2_ddr.data_read`|| ### CDC #16 #### Origin Flip-flop |Graph|Signal|Clock Domain|Flip-flop| |:---:|---|---|---| ||Signal: `u2_ddr.data_write2`
Usage:
- ddr_ctrl.vhd#286
- ddr_ctrl.vhd#293
- ddr_ctrl.vhd#296|CLK_50MHZ (falling)|TOP (plasma_3e) > u2_ddr (ddr_ctrl) > ddr_ctrl.vhd#284| #### Target Flip-flop |Graph|Signal|Clock Domain|Flip-flop| |:---:|---|---|---| ||Signal: `u2_ddr.data_read`
Usage:
- ddr_ctrl.vhd#277
- ddr_ctrl.vhd#279|CLK_50MHZ (rising)|TOP (plasma_3e) > u2_ddr (ddr_ctrl) > ddr_ctrl.vhd#263| ### CDC #18 #### Origin Flip-flop |Graph|Signal|Clock Domain|Flip-flop| |:---:|---|---|---| ||Signal: `u2_ddr.data_write2`
Usage:
- ddr_ctrl.vhd#286
- ddr_ctrl.vhd#293
- ddr_ctrl.vhd#296|CLK_50MHZ (falling)|TOP (plasma_3e) > u2_ddr (ddr_ctrl) > ddr_ctrl.vhd#284| #### Target Flip-flop |Graph|Signal|Clock Domain|Flip-flop| |:---:|---|---|---| ||Signal: `u2_ddr.data_read`
Usage:
- ddr_ctrl.vhd#277
- ddr_ctrl.vhd#279|CLK_50MHZ (rising)|TOP (plasma_3e) > u2_ddr (ddr_ctrl) > ddr_ctrl.vhd#263|
Back to Clock Domain Crossings (CDC) Report