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# CLK_50MHZ (falling) => clk_reg (rising) |Origin Clock Domain|Target Clock Domain|Number of CDCs|Graph| |---|---|---:|:---:| |CLK_50MHZ (falling)|clk_reg (rising)|2|| ## CDCs ### Summary |ID|Graph|Origin Signal|Target Signal|Details| |---:|:---:|---|---|:---:| |3||`u2_ddr.cycle_count2`|`u2_ddr.write_active`|| |4||`u2_ddr.cycle_count2`|`u2_ddr.write_prev`|| ### CDC #3 #### Origin Flip-flop |Graph|Signal|Clock Domain|Flip-flop| |:---:|---|---|---| ||Signal: `u2_ddr.cycle_count2`
Usage:
- ddr_ctrl.vhd#285
- ddr_ctrl.vhd#289|CLK_50MHZ (falling)|TOP (plasma_3e) > u2_ddr (ddr_ctrl) > ddr_ctrl.vhd#284| #### Target Flip-flop |Graph|Signal|Clock Domain|Flip-flop| |:---:|---|---|---| ||Signal: `u2_ddr.write_active`
Usage:
- ddr_ctrl.vhd#223
- ddr_ctrl.vhd#238
- ddr_ctrl.vhd#240|clk_reg (rising)|TOP (plasma_3e) > u2_ddr (ddr_ctrl) > ddr_ctrl.vhd#218| ### CDC #4 #### Origin Flip-flop |Graph|Signal|Clock Domain|Flip-flop| |:---:|---|---|---| ||Signal: `u2_ddr.cycle_count2`
Usage:
- ddr_ctrl.vhd#285
- ddr_ctrl.vhd#289|CLK_50MHZ (falling)|TOP (plasma_3e) > u2_ddr (ddr_ctrl) > ddr_ctrl.vhd#284| #### Target Flip-flop |Graph|Signal|Clock Domain|Flip-flop| |:---:|---|---|---| ||Signal: `u2_ddr.write_prev`
Usage:
- ddr_ctrl.vhd#222
- ddr_ctrl.vhd#232
- ddr_ctrl.vhd#234|clk_reg (rising)|TOP (plasma_3e) > u2_ddr (ddr_ctrl) > ddr_ctrl.vhd#218|
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