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# CLK_50MHZ (rising) => CLK_50MHZ (falling) |Origin Clock Domain|Target Clock Domain|Number of CDCs|Graph| |---|---|---:|:---:| |CLK_50MHZ (rising)|CLK_50MHZ (falling)|3|| ## CDCs ### Summary |ID|Graph|Origin Signal|Target Signal|Details| |---:|:---:|---|---|:---:| |9||`clk_reg`|`u2_ddr.byte_we_reg2`|| |14||`clk_reg`|`u2_ddr.data_write2`|| |33||`u2_ddr.cycle_count`|`u2_ddr.cycle_count2`|| ### CDC #9 #### Origin Flip-flop |Graph|Signal|Clock Domain|Flip-flop| |:---:|---|---|---| ||Signal: `clk_reg`
Usage:
- plasma_3e.vhd#164
- plasma_3e.vhd#166|CLK_50MHZ (rising)|TOP (plasma_3e) > plasma_3e.vhd#163| #### Target Flip-flop |Graph|Signal|Clock Domain|Flip-flop| |:---:|---|---|---| ||Signal: `u2_ddr.byte_we_reg2`
Usage:
- ddr_ctrl.vhd#287
- ddr_ctrl.vhd#294
- ddr_ctrl.vhd#297|CLK_50MHZ (falling)|TOP (plasma_3e) > u2_ddr (ddr_ctrl) > ddr_ctrl.vhd#284| ### CDC #14 #### Origin Flip-flop |Graph|Signal|Clock Domain|Flip-flop| |:---:|---|---|---| ||Signal: `clk_reg`
Usage:
- plasma_3e.vhd#164
- plasma_3e.vhd#166|CLK_50MHZ (rising)|TOP (plasma_3e) > plasma_3e.vhd#163| #### Target Flip-flop |Graph|Signal|Clock Domain|Flip-flop| |:---:|---|---|---| ||Signal: `u2_ddr.data_write2`
Usage:
- ddr_ctrl.vhd#286
- ddr_ctrl.vhd#293
- ddr_ctrl.vhd#296|CLK_50MHZ (falling)|TOP (plasma_3e) > u2_ddr (ddr_ctrl) > ddr_ctrl.vhd#284| ### CDC #33 #### Origin Flip-flop |Graph|Signal|Clock Domain|Flip-flop| |:---:|---|---|---| ||Signal: `u2_ddr.cycle_count`
Usage:
- ddr_ctrl.vhd#264
- ddr_ctrl.vhd#268
- ddr_ctrl.vhd#269
- ddr_ctrl.vhd#270
- ddr_ctrl.vhd#276
- ddr_ctrl.vhd#278|CLK_50MHZ (rising)|TOP (plasma_3e) > u2_ddr (ddr_ctrl) > ddr_ctrl.vhd#263| #### Target Flip-flop |Graph|Signal|Clock Domain|Flip-flop| |:---:|---|---|---| ||Signal: `u2_ddr.cycle_count2`
Usage:
- ddr_ctrl.vhd#285
- ddr_ctrl.vhd#289|CLK_50MHZ (falling)|TOP (plasma_3e) > u2_ddr (ddr_ctrl) > ddr_ctrl.vhd#284|
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