Back to Clock Domain Crossings (CDC) Report
# CLK_50MHZ (rising) => clk_reg (rising) |Origin Clock Domain|Target Clock Domain|Number of CDCs|Graph| |---|---|---:|:---:| |CLK_50MHZ (rising)|clk_reg (rising)|8|

| ## CDCs ### Summary |ID|Graph|Origin Signal|Target Signal|Details| |---:|:---:|---|---|:---:| |1|

|`u2_ddr.data_read`|`u1_plama.u1_cpu.u2_mem_ctrl.next_opcode_reg`|

| |2|

|`u2_ddr.data_read`|`u1_plama.u1_cpu.u2_mem_ctrl.next_opcode_reg`|

| |5|

|`u2_ddr.data_read`|`u1_plama.u1_cpu.u4_reg_bank.intr_enable_reg`|

| |6|

|`u2_ddr.data_read`|`u1_plama.u1_cpu.u4_reg_bank.intr_enable_reg`|

| |29|

|`u2_ddr.data_read`|`u1_plama.u1_cpu.u2_mem_ctrl.opcode_reg`|

| |30|

|`u2_ddr.data_read`|`u1_plama.u1_cpu.u2_mem_ctrl.opcode_reg`|

| |31|

|`u2_ddr.data_read`|`u1_plama.u2_ram.generic_ram.ram_proc.data`|

| |32|

|`u2_ddr.data_read`|`u1_plama.u2_ram.generic_ram.ram_proc.data`|

| ### CDC #1 #### Origin Flip-flop |Graph|Signal|Clock Domain|Flip-flop| |:---:|---|---|---| |

|Signal: `u2_ddr.data_read`
Usage:
- ddr_ctrl.vhd#277
- ddr_ctrl.vhd#279|CLK_50MHZ (rising)|TOP (plasma_3e) > u2_ddr (ddr_ctrl) > ddr_ctrl.vhd#263| #### Target Flip-flop |Graph|Signal|Clock Domain|Flip-flop| |:---:|---|---|---| |

|Signal: `u1_plama.u1_cpu.u2_mem_ctrl.next_opcode_reg`
Usage:
- mem_ctrl.vhd#168
- mem_ctrl.vhd#178|clk_reg (rising)|TOP (plasma_3e) > u1_plama (plasma) > u1_cpu (mlite_cpu) > u2_mem_ctrl (mem_ctrl) > mem_ctrl.vhd#165| ### CDC #2 #### Origin Flip-flop |Graph|Signal|Clock Domain|Flip-flop| |:---:|---|---|---| |

|Signal: `u1_plama.u1_cpu.u2_mem_ctrl.next_opcode_reg`
Usage:
- mem_ctrl.vhd#168
- mem_ctrl.vhd#178|clk_reg (rising)|TOP (plasma_3e) > u1_plama (plasma) > u1_cpu (mlite_cpu) > u2_mem_ctrl (mem_ctrl) > mem_ctrl.vhd#165| ### CDC #5 #### Origin Flip-flop |Graph|Signal|Clock Domain|Flip-flop| |:---:|---|---|---| |

|Signal: `u1_plama.u1_cpu.u4_reg_bank.intr_enable_reg`
Usage:
- reg_bank.vhd#90
- reg_bank.vhd#93
- reg_bank.vhd#95|clk_reg (rising)|TOP (plasma_3e) > u1_plama (plasma) > u1_cpu (mlite_cpu) > u4_reg_bank (reg_bank) > reg_bank.vhd#89| ### CDC #6 #### Origin Flip-flop |Graph|Signal|Clock Domain|Flip-flop| |:---:|---|---|---| |

|Signal: `u1_plama.u1_cpu.u4_reg_bank.intr_enable_reg`
Usage:
- reg_bank.vhd#90
- reg_bank.vhd#93
- reg_bank.vhd#95|clk_reg (rising)|TOP (plasma_3e) > u1_plama (plasma) > u1_cpu (mlite_cpu) > u4_reg_bank (reg_bank) > reg_bank.vhd#89| ### CDC #29 #### Origin Flip-flop |Graph|Signal|Clock Domain|Flip-flop| |:---:|---|---|---| |

|Signal: `u1_plama.u1_cpu.u2_mem_ctrl.opcode_reg`
Usage:
- mem_ctrl.vhd#167
- mem_ctrl.vhd#168
- mem_ctrl.vhd#176
- mem_ctrl.vhd#178|clk_reg (rising)|TOP (plasma_3e) > u1_plama (plasma) > u1_cpu (mlite_cpu) > u2_mem_ctrl (mem_ctrl) > mem_ctrl.vhd#165| ### CDC #30 #### Origin Flip-flop |Graph|Signal|Clock Domain|Flip-flop| |:---:|---|---|---| |

|Signal: `u1_plama.u1_cpu.u2_mem_ctrl.opcode_reg`
Usage:
- mem_ctrl.vhd#167
- mem_ctrl.vhd#168
- mem_ctrl.vhd#176
- mem_ctrl.vhd#178|clk_reg (rising)|TOP (plasma_3e) > u1_plama (plasma) > u1_cpu (mlite_cpu) > u2_mem_ctrl (mem_ctrl) > mem_ctrl.vhd#165| ### CDC #31 #### Origin Flip-flop |Graph|Signal|Clock Domain|Flip-flop| |:---:|---|---|---| |

|Signal: `u1_plama.u2_ram.generic_ram.ram_proc.data`
Usage:
- ram.vhd#67
- ram.vhd#71
- ram.vhd#74
- ram.vhd#77
- ram.vhd#80
- ram.vhd#85|clk_reg (rising)|TOP (plasma_3e) > u1_plama (plasma) > u2_ram (ram) > ram.vhd#65| ### CDC #32 #### Origin Flip-flop |Graph|Signal|Clock Domain|Flip-flop| |:---:|---|---|---| |