Back to Clock Domain Crossings (CDC) Report
# clk_reg (rising) => CLK_50MHZ (falling) |Origin Clock Domain|Target Clock Domain|Number of CDCs|Graph| |---|---|---:|:---:| |clk_reg (rising)|CLK_50MHZ (falling)|6|

| ## CDCs ### Summary |ID|Graph|Origin Signal|Target Signal|Details| |---:|:---:|---|---|:---:| |7|

|`u1_plama.u1_cpu.u2_mem_ctrl.byte_we_reg`|`u2_ddr.byte_we_reg2`|

| |8|

|`u1_plama.u1_cpu.u2_mem_ctrl.byte_we_reg`|`u2_ddr.byte_we_reg2`|

| |10|

|`u1_plama.u1_cpu.u2_mem_ctrl.opcode_reg`|`u2_ddr.data_write2`|

| |11|

|`u1_plama.u1_cpu.intr_signal`|`u2_ddr.data_write2`|

| |12|

|`u1_plama.u1_cpu.u2_mem_ctrl.opcode_reg`|`u2_ddr.data_write2`|

| |13|

|`u1_plama.u1_cpu.intr_signal`|`u2_ddr.data_write2`|

| ### CDC #7 #### Origin Flip-flop |Graph|Signal|Clock Domain|Flip-flop| |:---:|---|---|---| |

|Signal: `u1_plama.u1_cpu.u2_mem_ctrl.byte_we_reg`
Usage:
- mem_ctrl.vhd#170
- mem_ctrl.vhd#174|clk_reg (rising)|TOP (plasma_3e) > u1_plama (plasma) > u1_cpu (mlite_cpu) > u2_mem_ctrl (mem_ctrl) > mem_ctrl.vhd#165| #### Target Flip-flop |Graph|Signal|Clock Domain|Flip-flop| |:---:|---|---|---| |

|Signal: `u2_ddr.byte_we_reg2`
Usage:
- ddr_ctrl.vhd#287
- ddr_ctrl.vhd#294
- ddr_ctrl.vhd#297|CLK_50MHZ (falling)|TOP (plasma_3e) > u2_ddr (ddr_ctrl) > ddr_ctrl.vhd#284| ### CDC #8 #### Origin Flip-flop |Graph|Signal|Clock Domain|Flip-flop| |:---:|---|---|---| |

|Signal: `u2_ddr.byte_we_reg2`
Usage:
- ddr_ctrl.vhd#287
- ddr_ctrl.vhd#294
- ddr_ctrl.vhd#297|CLK_50MHZ (falling)|TOP (plasma_3e) > u2_ddr (ddr_ctrl) > ddr_ctrl.vhd#284| ### CDC #10 #### Origin Flip-flop |Graph|Signal|Clock Domain|Flip-flop| |:---:|---|---|---| |

|Signal: `u1_plama.u1_cpu.u2_mem_ctrl.opcode_reg`
Usage:
- mem_ctrl.vhd#167
- mem_ctrl.vhd#168
- mem_ctrl.vhd#176
- mem_ctrl.vhd#178|clk_reg (rising)|TOP (plasma_3e) > u1_plama (plasma) > u1_cpu (mlite_cpu) > u2_mem_ctrl (mem_ctrl) > mem_ctrl.vhd#165| #### Target Flip-flop |Graph|Signal|Clock Domain|Flip-flop| |:---:|---|---|---| |

|Signal: `u2_ddr.data_write2`
Usage:
- ddr_ctrl.vhd#286
- ddr_ctrl.vhd#293
- ddr_ctrl.vhd#296|CLK_50MHZ (falling)|TOP (plasma_3e) > u2_ddr (ddr_ctrl) > ddr_ctrl.vhd#284| ### CDC #11 #### Origin Flip-flop |Graph|Signal|Clock Domain|Flip-flop| |:---:|---|---|---| |

|Signal: `u1_plama.u1_cpu.intr_signal`
Usage:
- mlite_cpu.vhd#162
- mlite_cpu.vhd#173
- mlite_cpu.vhd#175|clk_reg (rising)|TOP (plasma_3e) > u1_plama (plasma) > u1_cpu (mlite_cpu) > mlite_cpu.vhd#160| #### Target Flip-flop |Graph|Signal|Clock Domain|Flip-flop| |:---:|---|---|---| |

|Signal: `u2_ddr.data_write2`
Usage:
- ddr_ctrl.vhd#286
- ddr_ctrl.vhd#293
- ddr_ctrl.vhd#296|CLK_50MHZ (falling)|TOP (plasma_3e) > u2_ddr (ddr_ctrl) > ddr_ctrl.vhd#284| ### CDC #12 #### Origin Flip-flop |Graph|Signal|Clock Domain|Flip-flop| |:---:|---|---|---| |

|Signal: `u2_ddr.data_write2`
Usage:
- ddr_ctrl.vhd#286
- ddr_ctrl.vhd#293
- ddr_ctrl.vhd#296|CLK_50MHZ (falling)|TOP (plasma_3e) > u2_ddr (ddr_ctrl) > ddr_ctrl.vhd#284| ### CDC #13 #### Origin Flip-flop |Graph|Signal|Clock Domain|Flip-flop| |:---:|---|---|---| |