Back to Clock Domains Report
# Clock Domain Details ## Summary | Name: Origin | Graph | Rising | Falling | Number of flip-flops
using this clock domain | Number of instances
using this clock domain | | --- | :---: | :---: | :---: | ---: | ---: | |**CLK_50MHZ**
  - **CLK_50MHZ**: plasma_3e.vhd#24 (Port)|Open Clock Hierarchy Graph|✔|✔|**10**/56 (17.86%)|**2**/15| ## Instances using this clock domain **Count: 2** | Instance | Rising | Falling | | --- | :---: | :---: | |TOP (plasma_3e)|✔|✗| |TOP (plasma_3e) > u2_ddr (ddr_ctrl)|✔|✔| ## Flip-flops using this clock domain **Count: 10** ### Rising-edge usage | Count: 5 | | --- | | ddr_ctrl.vhd#263 | | plasma_3e.vhd#163 | ### Falling-edge usage | Count: 5 | | --- | | ddr_ctrl.vhd#284 |
Note that there could be fewer source code locations than the number of flip-flops because several flip-flops can be inferred from the same piece of code.


Back to Clock Domains Report