# HDL1022: All reset domain crossings (RDC) should be reviewed ## Summary ```{raw} html

Count: 1

ReliabilitySecurityMaintainabilityCode attributeEffort to fixTags
HIGH--Intentionality | Logical0minsynthesis, rdc, bug-finder, linty-ultra
``` ## Description ```{raw} html

All reset domain crossings (RDC) of the design are listed for a manual review.

An issue is raised on each flip-flop whose reset is from a different clock domain that the clock domain of the flip-flop.

Noncompliant code example

entity fly is
  port (
    clk1 : in  std_logic;
    clk2 : in  std_logic;
    rst  : in  std_logic;
    i1   : in  std_logic;
    o1   : out std_logic
  );
end entity;

architecture rtl of fly is
  signal rst1 : std_logic;
begin
  process (rst) is
  begin
    if rst = '1' then
      rst1 <= '0';
    elsif rising_edge(clk1) then
      rst1 <= '1';
    end if;
  end process;

  process (rst1) is
  begin
    -- 'rst1' is from 'clk1' clock domain that is different from 'clk2' flip-flop clock domain
    if rst1 = '1' then
      o1 <= '0';
    elsif rising_edge(clk2) then
      o1 <= i1;
    end if;
  end process;
end architecture;
``` ## Parameters No parameters. ```{raw} html ```