```{raw} html ``` # 05a646b5-bde9-4426-a10b-2cfcd92a6c39 ## Summary ```{raw} html

Count: 1

RuleMessageLocationEffortReliabilitySecurityMaintainability
VHDL1061Rename this clock signal to preserve its name across the design. Source signal name: CLK_50MHZ.mlite_cpu.vhd#8030minMEDIUM-HIGH
``` ```{raw} html ```