```{raw} html ``` # 3607a0a9-e29f-44bc-8ede-a48d44e99cc8 ## Summary ```{raw} html

Count: 1

RuleMessageLocationEffortReliabilitySecurityMaintainability
VHDL1061Rename this clock signal to preserve its name across the design. Source signal name: CLK_50MHZ.uart.vhd#2330minMEDIUM-HIGH
``` ```{raw} html ```