```{raw} html ``` # 39256af3-05ec-4914-ab42-3b05209bf59a ## Summary ```{raw} html
| Rule | Message | Location | Effort | Reliability | Security | Maintainability |
|---|---|---|---|---|---|---|
| HDL1001 | Review clock domain crossing between 'u2_ddr.cycle_count' (target) and 'u1_plama.u1_cpu.u2_mem_ctrl.byte_we_reg' (origin) | 0min | HIGH | - | - |