```{raw} html ``` # 42ef3f97-b08a-41cd-8acf-398ccae016c5 ## Summary ```{raw} html
| Rule | Message | Location | Effort | Reliability | Security | Maintainability |
|---|---|---|---|---|---|---|
| VHDL1062 | Rename this reset signal to preserve its name across the design. Source signal name: CLK_50MHZ. | 30min | MEDIUM | - | HIGH |