```{raw} html ``` # 50686f79-d0b8-41aa-a5f7-c2b87a0bcd3f ## Summary ```{raw} html
| Rule | Message | Location | Effort | Reliability | Security | Maintainability |
|---|---|---|---|---|---|---|
| HDL1051 | Synchronize the release of asynchronous reset 'u1_plama.reset' into clock domain 'u2_ddr.clk_2x' with at least 2 flip-flops. | 30min | HIGH | - | - |