```{raw} html ``` # 67f5084a-c6bd-4a8b-94a3-1fe28d2a7402 ## Summary ```{raw} html
| Rule | Message | Location | Effort | Reliability | Security | Maintainability |
|---|---|---|---|---|---|---|
| VHDL1062 | Rename this reset signal to preserve its name across the design. Source signal name: CLK_50MHZ. | 30min | MEDIUM | - | HIGH |