```{raw} html ``` # 911c5777-6598-46b5-be62-a8447982899a ## Summary ```{raw} html

Count: 1

RuleMessageLocationEffortReliabilitySecurityMaintainability
HDL1001Review clock domain crossing between 'u2_ddr.data_write2' (target) and 'u1_plama.u1_cpu.intr_signal' (origin)ddr_ctrl.vhd#2880minHIGH--
``` ```{raw} html ```