```{raw} html ``` # 911c5777-6598-46b5-be62-a8447982899a ## Summary ```{raw} html
| Rule | Message | Location | Effort | Reliability | Security | Maintainability |
|---|---|---|---|---|---|---|
| HDL1001 | Review clock domain crossing between 'u2_ddr.data_write2' (target) and 'u1_plama.u1_cpu.intr_signal' (origin) | 0min | HIGH | - | - |