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Count: 1

RuleMessageLocationEffortReliabilitySecurityMaintainability
HDL1001Review clock domain crossing between 'u2_ddr.byte_we_reg2' (target) and 'u1_plama.u1_cpu.u2_mem_ctrl.byte_we_reg' (origin)ddr_ctrl.vhd#2880minHIGH--
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