```{raw} html ``` # ef37dce4-e2f7-4c32-9999-aefc8f15d96d ## Summary ```{raw} html
| Rule | Message | Location | Effort | Reliability | Security | Maintainability |
|---|---|---|---|---|---|---|
| HDL1001 | Review clock domain crossing between 'u1_plama.u1_cpu.u2_mem_ctrl.opcode_reg' (target) and 'u2_ddr.data_read' (origin) | 0min | HIGH | - | - |