# VERILOG022: Branching preprocessor directives should be aligned to the left ## Summary ```{raw} html

Reliability	Security	Maintainability	Code attribute	Effort to fix	Tags

-	-	LOW	Consistency \| Formatted	2min	synthesis, vscode, lowrisc, linter, simulation

``` ## Description ```{raw} html

Articles & blog posts

lowRISC Verilog Coding Style Guide - Indentation - Preprocessor Directives

Branching preprocessor directives ( `ifdef, `ifndef, `else, `elsif , `endif) should be aligned to the left, even if they are nested. The objective is to easily spot those conditional directives.

Noncompliant code example

package my_package;
  `ifdef FOO
    parameter bit ABC = 1;
  `else
    parameter bit ABC = 2;
  `endif
endpackage : my_package

Compliant solution

package my_package;
`ifdef FOO
  parameter bit ABC = 1;
`else
  parameter bit ABC = 2;
`endif
endpackage : my_package

``` ## Parameters No parameters. ```{raw} html ```