# VERILOG048: "always_comb" should be used instead of "always @*" ## Summary ```{raw} html
| Reliability | Security | Maintainability | Code attribute | Effort to fix | Tags |
|---|---|---|---|---|---|
| - | - | MEDIUM | Consistency | Conventional | 10min | synthesis, vscode, lowrisc, simulation, linter, deprecated |
always @(*) begin b <= a; c <= b; end always @* begin d <= f; e <= g; end
always_comb begin b <= a; c <= b; end always_comb begin d <= f; e <= g; end
SystemVerilog always_comb should be used instead of Verilog always @* or always
@(*).