# VERILOG2005: An "inout" port that is never read should be converted into an "output" port ## Summary ```{raw} html

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ReliabilitySecurityMaintainabilityCode attributeEffort to fixTags
MEDIUM--Intentionality | Logical10minsynthesis, vscode, linter, simulation
``` ## Description ```{raw} html

Noncompliant code example

module fly(inout x);
  assign x = 1;
endmodule

Compliant solution

module fly(output x);
  assign x = 1;
endmodule

An inout port that is never read should be converted into an output port.

``` ## Parameters No parameters. ```{raw} html ```