# VERILOG2010: Unused implicitly created nets should be removed ## Summary ```{raw} html

Count: 1

ReliabilitySecurityMaintainabilityCode attributeEffort to fixTags
HIGH--Intentionality | Logical10minsynthesis, vscode, simulation, linter
``` ## Description ```{raw} html

An implicitly created net is not referenced elsewhere in the design. This is often a typo in the name and not intentional.

Noncompliant code example

module fly(output x);
  assign x = 1;
endmodule

module top;
  logic typo;
  fly fly1(typa); // Noncompliant: 'typa' instead of 'typo'
endmodule

Compliant solution

module fly(output x);
  assign x = 1;
endmodule

module top;
  logic typo;
  fly fly1(typo);
endmodule
``` ## Parameters No parameters. ```{raw} html ```