# VERILOG2014: An output port that is never given a value should be removed ## Summary ```{raw} html

Count: 1

ReliabilitySecurityMaintainabilityCode attributeEffort to fixTags
MEDIUM--Intentionality | Logical10minsynthesis, vscode, linter, simulation, dead-code
``` ## Description ```{raw} html

Noncompliant code example

module fly(
  input x,
  output y // Noncompliant: Output port 'y' is never given a value
);
endmodule

An output port that is never given a value should be removed.

``` ## Parameters No parameters. ```{raw} html ```