# VERILOG2025: Procedurally force a bit-select or range select of a variable should not be used ## Summary ```{raw} html

Reliability	Security	Maintainability	Code attribute	Effort to fix	Tags

LOW	-	-	Intentionality \| Logical	10min	synthesis, portability, vscode, linter, simulation

``` ## Description ```{raw} html

Noncompliant code example

module top;
  int i;
  initial begin
    force i[1] = 1; // Noncompliant
    release i[1]; // Noncompliant
  end
endmodule

According to the Verilog/SystemVerilog standard, it is illegal to procedurally force/release a bit-select or range select of a variable (you can do that with a net, or with a plain variable).

Even if some tools support this syntax, it should be avoided to keep your code portable.

``` ## Parameters No parameters. ```{raw} html ```