# VERILOG2037: Duplicated timing paths should be removed ## Summary ```{raw} html

Count: 1

ReliabilitySecurityMaintainabilityCode attributeEffort to fixTags
HIGH--Intentionality | Logical10minsynthesis, vscode, simulation, linter
``` ## Description ```{raw} html

More than one specify timing path was given for a particular pair of input and output terminals in a module.

Duplicated timing paths should be removed.

Noncompliant code example

module fly(input a, output b);
  specify
    (a => b) = 1;
    (a => b) = 2; // Noncompliant
  endspecify
endmodule

Compliant solution

module fly(input a, output b);
  specify
    (a => b) = 1;
  endspecify
endmodule
``` ## Parameters No parameters. ```{raw} html ```