# VERILOG2044: Empty assignment pattern literals should not be used ## Summary ```{raw} html

Count: 1

ReliabilitySecurityMaintainabilityCode attributeEffort to fixTags
--LOWIntentionality | Clear5minsynthesis, portability, vscode, linter, simulation
``` ## Description ```{raw} html

Noncompliant code example

int foo[] = '{};

Even if it is supported by some tools, empty assignment pattern literals are not allowed by SystemVerilog standard. Refrain using such a syntax to keep your code portable.

``` ## Parameters No parameters. ```{raw} html ```