# VERILOG2059: Formatting multi-bit nets with the "%v" specifier should be avoided ## Summary ```{raw} html

Count: 1

ReliabilitySecurityMaintainabilityCode attributeEffort to fixTags
LOW--Consistency | Conventional5minportability, synthesis, vscode, linter, simulation
``` ## Description ```{raw} html

Formatting multi-bit nets with the %v specifier is not allowed in SystemVerilog.

Even if most tools allow it, refrain from using this syntax to keep your code portable.

Noncompliant code example

module fly;
  wire [3:0] w;
  initial $display("%v", w);
endmodule
``` ## Parameters No parameters. ```{raw} html ```