# VERILOG2061: Implicit conversions between two unrelated types should be avoided ## Summary ```{raw} html

Count: 1

ReliabilitySecurityMaintainabilityCode attributeEffort to fixTags
HIGH--Intentionality | Logical10minsynthesis, vscode, linter, simulation
``` ## Description ```{raw} html

An implicit conversion in an expression converts between two unrelated types. SystemVerilog allows this for all packed integral types but it often indicates a mistake in the code.

Noncompliant code example

module fly;
  struct packed { logic a; int b; } foo;
  union packed { int a; int b; } bar;
  initial foo = bar;
endmodule
``` ## Parameters No parameters. ```{raw} html ```