# VERILOG2072: Timing control edge expression should not be wider than one bit ## Summary ```{raw} html

Count: 1

ReliabilitySecurityMaintainabilityCode attributeEffort to fixTags
HIGH--Intentionality | Logical10minsynthesis, vscode, simulation, linter
``` ## Description ```{raw} html

Noncompliant code example

module fly;
  int i;
  always @(posedge i) begin end
endmodule

Compliant solution

module fly;
  logic i;
  always @(posedge i) begin end
endmodule

A timing control edge expression (posedge, negedge, etc.) is wider than one bit, which can indicate a mistake since only changes to the first bit will trigger the edge.

``` ## Parameters No parameters. ```{raw} html ```