# VERILOG2077: "dist" constraint items should not be surrounded by parentheses ## Summary ```{raw} html

Reliability	Security	Maintainability	Code attribute	Effort to fix	Tags

MEDIUM	-	-	Intentionality \| Logical	5min	portability, synthesis, vscode, linter, simulation

``` ## Description ```{raw} html

class Fly;
  rand bit a;
  rand bit [3:0] b;
  constraint cmd_c {
    a -> (b dist { 0 := 1, [1:15] := 1});
  }
endclass

class Fly;
  rand bit a;
  rand bit [3:0] b;
  constraint cmd_c {
    a -> b dist { 0 := 1, [1:15] := 1};
  }
endclass

dist constraint items are not allowed to be surrounded by parentheses according to the SystemVerilog standard.

Even if some tools allow it, refrain from using this syntax to keep your code portable.

``` ## Parameters No parameters. ```{raw} html ```