# VERILOG2080: Standalone "generate" blocks without a corresponding generate loop or condition should not be used ## Summary ```{raw} html

Reliability	Security	Maintainability	Code attribute	Effort to fix	Tags

MEDIUM	-	-	Intentionality \| Logical	5min	synthesis, vscode, linter, simulation, deprecated

``` ## Description ```{raw} html

Noncompliant code example

module fly;
  begin : gen_block // Noncompliant
    int i = 1;
  end
endmodule

Standalone generate blocks (begin / end pair) without a corresponding generate loop or condition were allowed in older Verilog standards but is no longer allowed in SystemVerilog.

``` ## Parameters No parameters. ```{raw} html ```