# VERILOG2096: An implicit conversion should not change the signedness of an integer type ## Summary ```{raw} html

Count: 1

ReliabilitySecurityMaintainabilityCode attributeEffort to fixTags
HIGH--Intentionality | Logical5minsynthesis, vscode, simulation, linter
``` ## Description ```{raw} html

An implicit conversion changes the signedness of an integer type (from signed to unsigned or vice versa), which can lead to unexpected behaviors.

Noncompliant code example

module fly;
  logic signed [31:0] a;
  logic [31:0] b;
  assign b = a;
endmodule

Compliant solution

module fly;
  logic signed [31:0] a;
  logic signed [31:0] b;
  assign b = a;
endmodule
``` ## Parameters No parameters. ```{raw} html ```