# VERILOG2098: Parameters should not be used inside "specify" blocks ## Summary ```{raw} html

Count: 1

ReliabilitySecurityMaintainabilityCode attributeEffort to fixTags
LOW--Consistency | Conventional10minsynthesis, portability, vscode, linter, simulation
``` ## Description ```{raw} html

Noncompliant code example

module fly(input [1:0] a, output [1:0] b);
  parameter p = 1;
  specify
    (a[p] => b[0]) = 1;
  endspecify
endmodule

Compliant solution

module fly(input [1:0] a, output [1:0] b);
  specify
    (a[1] => b[0]) = 1;
  endspecify
endmodule

The SystemVerilog standard disallows using parameters inside of specify blocks.

Even if most tools allow them, stick to the standard to keep your code portable.

``` ## Parameters No parameters. ```{raw} html ```