# VHDL036: Vector direction in ranges should always be the same ## Summary ```{raw} html

Reliability	Security	Maintainability	Code attribute	Effort to fix	Tags

-	-	LOW	Consistency \| Conventional	2min	synthesis, do254, vscode, linter, simulation, cnes, cnes-std-06100, do254-ss21

``` ## Description ```{raw} html

With default useDownto parameter value: true

architecture a of e is
  signal a : std_logic_vector(0 to 1) -- Noncompliant: Use 'downto' instead
begin
  ...
end;

With default useDownto parameter value: true

architecture a of e is
  signal a : std_logic_vector(1 downto 0)
begin
  ...
end;

Using different vector directions in ranges makes the code harder to read and understand.

``` ## Parameters ```{raw} html

Parameter	Value	Description

useDownto	true	Set to true to check vector directions are 'DOWNTO'. When set to false, vector directions 'TO' are checked.

``` ```{raw} html ```