# VHDL1012: Clock signals not used as clock of a flip-flop should be reviewed ## Summary ```{raw} html

Count: 1

ReliabilitySecurityMaintainabilityCode attributeEffort to fixTags
HIGH--Intentionality | Logical20mincnes-custom, synthesis, bug-finder, do254, cnes, do254-ss8, cnes-custom-cne-04900, cnes-std-04500, clock, do254-ss9, linty-ultra
``` ## Description ```{raw} html

Clock signals should not be reused in a non-clock way. This rule raises an issue each time a clock signal is used in a way that is different from defining a flip-flop.

Noncompliant code example

process(clk, rst) is
begin
  if rst = '1' then
    clk <= '0'; -- Noncompliant: 'clk' clock signal is reused in a non-clock way
  elsif rising_edge(clk) then -- Compliant: Defining a flip-flop
    s <= '0';
  end if;
end process;
``` ## Parameters No parameters. ```{raw} html ```