# VHDL1013: "rising_edge" and "falling_edge" functions should be used to detect clock transitions ## Summary ```{raw} html

Count: 1

ReliabilitySecurityMaintainabilityCode attributeEffort to fixTags
MEDIUM--Intentionality | Logical10minsynthesis, bug-finder, clock, linty-ultra
``` ## Description ```{raw} html

To improve reliability, use rising_edge and falling_edge functions instead of other clock transition implementations such as:

Articles & blog posts

Noncompliant code example

process(clk) is
begin
  if clk'event and clk='1' then -- Noncompliant
    o1 <= not i1;
  end if;
end process;

Compliant solution

process(clk) is
begin
  if rising_edge(clk) then -- Compliant
    o1 <= not i1;
  end if;
end process;
``` ## Parameters No parameters. ```{raw} html ```