# VHDL1015: Processes should only use one edge transition direction per clock ## Summary ```{raw} html

Reliability	Security	Maintainability	Code attribute	Effort to fix	Tags

MEDIUM	-	-	Intentionality \| Logical	20min	synthesis, bug-finder, clock, linty-ultra

``` ## Description ```{raw} html

An issue is raised when multiple edge transition directions are used for a clock within the same process.

Noncompliant code example

p1 : process (clk) is -- Noncompliant: rising and falling
begin
  if rising_edge(clk) then
    s <= not s;
  end if;
  if falling_edge(clk) then
    s <= s;
  end if;
end process;

Compliant solution

p1 : process (clk) is
begin
  if rising_edge(clk) then
    s <= not s;
  end if;
end process;

p2 : process (clk) is
begin
  if falling_edge(clk) then
    s <= s;
  end if;
end process;

``` ## Parameters No parameters. ```{raw} html ```