# VHDL1037: The sensitivity list of a process should be minimal ## Summary ```{raw} html

Reliability	Security	Maintainability	Code attribute	Effort to fix	Tags

MEDIUM	-	-	Intentionality \| Complete	5min	synthesis, bug-finder, do254, cnes-std-05000, cnes, cnes-std-05300, latch, cnes-std-05500, do254-cp8, linty-ultra

``` ## Description ```{raw} html

The sensitivity list of a process should be minimal to not slow down simulation:

Clocked process with no reset: Clocks only
Clocked process with synchronous Resets only: clocks only
Clocked process with asynchronous Resets only: clocks and asynchronous resets only
Clocked process with both synchronous and asynchronous resets: Clocks and asynchronous resets only
Clocked or combinational process: Duplicated entries in the sensitivity list should be removed

To check for incomplete sensitivity list, activate The sensitivity list of a process should be complete

Noncompliant code example

-- Clocked process with asynchronous reset
process (clk) is -- Noncompliant: Missing 'rst'
begin
  if rst = '1' then
    q <= '0';
  elsif rising_edge(clk) then
    q <= d;
  end if;
end process;

-- Clocked process with synchronous reset
process (rst) is -- Noncompliant: Should be 'clk' instead of 'rst'
begin
  if rising_edge(clk) then
    if rst = '1' then
      q <= '0';
    else
      q <= d;
    end if;
  end if;
end process;

process (y, z, y) is -- Noncompliant: 'y' should be removed
begin
   q <= y or z;
end process;

Compliant solution

-- Clocked process with asynchronous reset
process(clk, rst) is
begin
  if rst = '1' then
    q <= '0';
  elsif rising_edge(clk) then
    q <= d;
  end if;
end process;

-- Clocked process with synchronous reset
process(clk) is
begin
  if rising_edge(clk) then
    if rst = '1' then
      q <= '0';
    else
      q <= d;
    end if;
  end if;
end process;

process (y, z) is
begin
   q <= y or z;
end process;

``` ## Parameters No parameters. ```{raw} html ```