# VHDL1067: Range should not be empty ## Summary ```{raw} html
| Reliability | Security | Maintainability | Code attribute | Effort to fix | Tags |
|---|---|---|---|---|---|
| HIGH | - | - | Intentionality | Logical | 20min | synthesis, bug-finder, linty-ultra |
An empty range is likely a coding mistake. There is no reason for a range to be empty.
i0 : in std_logic_vector(7 to 0);
i0 : in std_logic_vector(0 to 7);``` ## Parameters No parameters. ```{raw} html ```