# VHDL1067: Range should not be empty ## Summary ```{raw} html

Count: 1

ReliabilitySecurityMaintainabilityCode attributeEffort to fixTags
HIGH--Intentionality | Logical20minsynthesis, bug-finder, linty-ultra
``` ## Description ```{raw} html

An empty range is likely a coding mistake. There is no reason for a range to be empty.

Noncompliant code example

i0 : in std_logic_vector(7 to 0);

Compliant solution

i0 : in std_logic_vector(0 to 7);
``` ## Parameters No parameters. ```{raw} html ```