# VHDL136: All references should have the same case as the corresponding declarations ## Summary ```{raw} html

Reliability	Security	Maintainability	Code attribute	Effort to fix	Tags

-	-	MEDIUM	Intentionality \| Clear	5min	synthesis, do254, vscode, do254-dr2, linter, simulation

``` ## Description ```{raw} html

Noncompliant code example

procedure proc is
  variable tmp : std_ulogic := '0';
  constant cst : std_ulogic := '0';
begin
  tmp <= Cst; -- Noncompliant: Wrong case for identifier "Cst". Should be "cst" instead.
end PROC;     -- Noncompliant: Wrong case for identifier "PROC". Should be "proc" instead.

Compliant solution

procedure proc is
  variable tmp : std_ulogic := '0';
  constant cst : std_ulogic := '0';
begin
  tmp <= cst;
end proc;

All references should have the same case as the corresponding declarations. This is a convention rule since VHDL is not case-sensitive.

``` ## Parameters No parameters. ```{raw} html ```