# VHDL138: All output ports (and optionally all input ports) of a component should be mapped ## Summary ```{raw} html

Count: 1

ReliabilitySecurityMaintainabilityCode attributeEffort to fixTags
MEDIUM--Intentionality | Complete20minsynthesis, do254, do254-cp11, do254-cp12, vscode, linter, simulation, cnes, cnes-std-03200
``` ## Description ```{raw} html

All output ports of a component should be mapped. Unused ports can be mapped with the open keyword.

Noncompliant code example

architecture a of e is
  signal sa : std_logic;
  signal sb : std_logic;
  signal sx : std_logic;
  signal sy : std_logic;

  component comp
    port(
      a : in bit;
      b : in bit;
      x : out bit;
      y : out bit
    );
  end component;

begin
  g: comp port map (a => sa, b => sb, x => sx); -- Noncompliant: "y" is not mapped
end;

Compliant solution

architecture a of e is
  signal sa : std_logic;
  signal sb : std_logic;
  signal sx : std_logic;
  signal sy : std_logic;

  component comp
    port(
      a : in bit;
      b : in bit;
      x : out bit;
      y : out bit
    );
  end component;

begin
  g: comp port map (a => sa, b => sb, x => sx, y => sy); -- Compliant: "a", "b", "x" and "y" are mapped
end;

architecture a of e is
  signal sa : std_logic;
  signal sb : std_logic;
  signal sx : std_logic;
  signal sy : std_logic;

  component comp
    port(
      a : in bit;
      b : in bit;
      x : out bit;
      y : out bit
    );
  end component;

begin
  g: comp port map (a => sa, b => sb, x => sx, y => open); -- Compliant: "open" is used
end;
``` ## Parameters ```{raw} html

Count: 1

ParameterValueDescription
checkInputPortsfalseSet to 'true' to also check that input ports are mapped. Set to 'false' otherwise.
``` ```{raw} html ```