# VHDL157: std_logic_vector signals should define a range ## Summary ```{raw} html

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ReliabilitySecurityMaintainabilityCode attributeEffort to fixTags
LOW--Intentionality | Logical5minsynthesis, vscode, simulation, linter
``` ## Description ```{raw} html

Noncompliant code example

signal sig : std_logic_vector; -- Noncompliant: Range not set

Compliant solution

signal sig : std_logic_vector(2 downto 0);

This rule raises an issue if an std_logic_vector does not define a range.

``` ## Parameters No parameters. ```{raw} html ```