# VHDL164: Range direction in array definitions should always be the same ## Summary ```{raw} html

Reliability	Security	Maintainability	Code attribute	Effort to fix	Tags

-	-	LOW	Consistency \| Conventional	2min	synthesis, vscode, cnes-std-06000, simulation, linter, cnes

``` ## Description ```{raw} html

Noncompliant code example

With default useTo parameter value: true

architecture a of e is
  type my_type is array (3 downto 0) of std_logic;
begin
end;

Compliant solution

With default useTo parameter value: true

architecture a of e is
  type my_type is array (0 to 3) of std_logic;
begin
end;

Use different range direction in array definitions makes the code harder to read and understand. By default, using increasing index with to keyword is recommended.

``` ## Parameters ```{raw} html

Parameter	Value	Description

useTo	true	Set to true to check range directions in array definitions are 'TO'. When set to false, range directions 'DOWNTO' are checked.

``` ```{raw} html ```