# VHDL215: Ports should be mapped with explicit mapping ## Summary ```{raw} html

Reliability	Security	Maintainability	Code attribute	Effort to fix	Tags

MEDIUM	-	LOW	Intentionality \| Clear	5min	synthesis, vscode, linter, simulation

``` ## Description ```{raw} html

To improve code readability, ports should be mapped with explicit mapping.

Noncompliant code example

architecture a of e is
  signal sa : std_logic;
  signal sb : std_logic;
  signal sx : std_logic;
  signal sy : std_logic;

  component comp
    port(
      a : in bit;
      b : in bit;
      x : out bit;
      y : out bit
    );
  end component;

begin
  g: comp port map (sa, sb, sx, sy); -- Noncompliant
end;

Compliant solution

architecture a of e is
  signal sa : std_logic;
  signal sb : std_logic;
  signal sx : std_logic;
  signal sy : std_logic;

  component comp
    port(
      a : in bit;
      b : in bit;
      x : out bit;
      y : out bit
    );
  end component;

begin
  g: comp port map (a => sa, b => sb, x => sx, y => sy); -- Compliant
end;

``` ## Parameters No parameters. ```{raw} html ```