# VHDL229: Global signals should not be used in design ## Summary ```{raw} html

Count: 1

ReliabilitySecurityMaintainabilityCode attributeEffort to fixTags
HIGH--Intentionality | Logical10minsynthesis, vscode, linter
``` ## Description ```{raw} html

Noncompliant code example

package my_package is
  signal global_signal : std_logic := '0';
end;

Global signals cannot be used in design as they cannot be synthesized.

``` ## Parameters No parameters. ```{raw} html ```