# VHDL303: Only synthesizable and allowed types should be used in design ## Summary ```{raw} html
| Reliability | Security | Maintainability | Code attribute | Effort to fix | Tags |
|---|---|---|---|---|---|
| HIGH | - | - | Intentionality | Logical | 20min | synthesis, linter, cnes, cnes-std-05800 |
Restrict the usage of allowed types in your design:
bitbit_vectorintegernaturalpositivesignedstd_logicstd_logic_vectorstd_ulogicstd_ulogic_vectorunsignedArray of those types and record of those types are also allowed.
Additional types are allowed for generics:
booleanNote that the list of allowed types can be customized through parameters.
integer,signed,std_logic,std_logic_vector,unsigned
architecture a of e is
signal s : bit; -- Noncompliant
constant c : bit; -- Noncompliant
type my_record_type is record
a : bit;
b : std_logic;
end record;
signal r : my_record_type; -- Noncompliant: See above record has 'bit' type
type my_array_type is array(3 downto 0) of bit;
signal a : my_array_type; -- Noncompliant: See above array type of 'bit'
begin
process is
variable v : bit; -- Noncompliant
begin
end process;
end;
integer,signed,std_logic,std_logic_vector,unsigned
architecture a of e is
signal s : std_logic;
constant c : std_logic;
type my_record_type is record
a : std_logic;
b : std_logic;
end record;
signal r : my_record_type;
type my_array_type is array(3 downto 0) of std_logic;
signal a : my_array_type;
begin
process is
variable v : std_logic;
begin
end process;
end;
```
## Parameters
```{raw} html
| Parameter | Value | Description |
|---|---|---|
| allowAllEnumeratedTypes | true | Set to 'true' to allow all enumerated types. Set to 'false' otherwise. |
| allowedTypes | bit,bit_vector,integer,natural,positive,signed,std_logic,std_logic_vector,std_ulogic,std_ulogic_vector,unsigned | Comma separated list of allowed types. |
| additionalAllowedTypesForGeneric | boolean | Comma separated list of additional allowed types for generics. |