# VHDL305: "while" loops should not be used for synthesis ## Summary ```{raw} html
| Reliability | Security | Maintainability | Code attribute | Effort to fix | Tags |
|---|---|---|---|---|---|
| - | - | MEDIUM | Intentionality | Logical | 20min | synthesis, vscode, linter |
Some tools do not support while loops for synthesis. Thus, for better portability, use for
loops instead.
while i < 100 loop ... end loop;
for i in 0 to 100 loop ... end loop;``` ## Parameters No parameters. ```{raw} html ```