# VHDL323: Only one generic should be declared or mapped per line ## Summary ```{raw} html

Count: 1

ReliabilitySecurityMaintainabilityCode attributeEffort to fixTags
--LOWIntentionality | Clear5minsynthesis, vscode, linter, simulation
``` ## Description ```{raw} html

Declaring multiple items on a single line reduces readability.

This rule enforces that there is at most one generic declaration or mapping per line.

Noncompliant code example

component my_component
  generic (
    a, b : in std_logic
  );
end component;

i1: comp generic map (
  a => '0', b => '0'
);

Compliant solution

component my_component
  generic (
    a : in std_logic;
    b : in std_logic
  );
end component;

i1: comp generic map (
  a => '0',
  b => '0'
);
``` ## Parameters No parameters. ```{raw} html ```