Back to Design Hierarchy Report
# Entity - plasma_3e ## Summary | Name | Location | Description | | --- | --- | --- | |plasma_3e|plasma_3e.vhd#19|| ## Instantiations Count: 1 | Name | Location | Description | Details | | --- | --- | --- | :---: | | TOP | plasma_3e.vhd#19 | | View Instantiation Details | ## Generics Count: 4 | Name | Type | Default value | Description | | --- | --- | --- | --- | |memory_type|string|"DUAL_PORT_"|| |log_file|string|"UNUSED"|| |ethernet|std_logic|'0'|| |use_cache|std_logic|'1'|| ## Ports Count: 49 | Name | Mode | Type | Description | | --- | --- | --- | --- | |CLK_50MHZ|in|std_logic|| |RS232_DCE_RXD|in|std_logic|| |RS232_DCE_TXD|out|std_logic|| |SD_CK_P|out|std_logic|| |SD_CK_N|out|std_logic|| |SD_CKE|out|std_logic|| |SD_BA|out|std_logic_vector ( 1 downto 0 )|| |SD_A|out|std_logic_vector ( 12 downto 0 )|| |SD_CS|out|std_logic|| |SD_RAS|out|std_logic|| |SD_CAS|out|std_logic|| |SD_WE|out|std_logic|| |SD_DQ|inout|std_logic_vector ( 15 downto 0 )|| |SD_UDM|out|std_logic|| |SD_UDQS|inout|std_logic|| |SD_LDM|out|std_logic|| |SD_LDQS|inout|std_logic|| |E_MDC|out|std_logic|| |E_MDIO|inout|std_logic|| |E_RX_CLK|in|std_logic|| |E_RX_DV|in|std_logic|| |E_RXD|in|std_logic_vector ( 3 downto 0 )|| |E_TX_CLK|in|std_logic|| |E_TX_EN|out|std_logic|| |E_TXD|out|std_logic_vector ( 3 downto 0 )|| |SF_CE0|out|std_logic|| |SF_OE|out|std_logic|| |SF_WE|out|std_logic|| |SF_BYTE|out|std_logic|| |SF_STS|in|std_logic|| |SF_A|out|std_logic_vector ( 24 downto 0 )|| |SF_D|inout|std_logic_vector ( 15 downto 1 )|| |SPI_MISO|inout|std_logic|| |VGA_VSYNC|out|std_logic|| |VGA_HSYNC|out|std_logic|| |VGA_RED|out|std_logic|| |VGA_GREEN|out|std_logic|| |VGA_BLUE|out|std_logic|| |PS2_CLK|in|std_logic|| |PS2_DATA|in|std_logic|| |LED|out|std_logic_vector ( 7 downto 0 )|| |ROT_CENTER|in|std_logic|| |ROT_A|in|std_logic|| |ROT_B|in|std_logic|| |BTN_EAST|in|std_logic|| |BTN_NORTH|in|std_logic|| |BTN_SOUTH|in|std_logic|| |BTN_WEST|in|std_logic|| |SW|in|std_logic_vector ( 3 downto 0 )||
Back to Design Hierarchy Report