Back to Design Hierarchy Report
# Entity - cache ## Summary | Name | Location | Description | | --- | --- | --- | |cache|cache.vhd#21|| ## Instantiations Count: 1 | Name | Location | Description | Details | | --- | --- | --- | :---: | | opt_cache2.u_cache | plasma.vhd#151 | | View Instantiation Details | ## Generics Count: 1 | Name | Type | Default value | Description | | --- | --- | --- | --- | |memory_type|string|"DEFAULT"|| ## Ports Count: 9 | Name | Mode | Type | Description | | --- | --- | --- | --- | |clk|in|std_logic|| |reset|in|std_logic|| |address_next|in|std_logic_vector ( 31 downto 2 )|| |byte_we_next|in|std_logic_vector ( 3 downto 0 )|| |cpu_address|in|std_logic_vector ( 31 downto 2 )|| |mem_busy|in|std_logic|| |cache_access|out|std_logic|| |cache_checking|out|std_logic|| |cache_miss|out|std_logic||
Back to Design Hierarchy Report