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# Entity - mem_ctrl ## Summary | Name | Location | Description | | --- | --- | --- | |mem_ctrl|mem_ctrl.vhd#17|| ## Instantiations Count: 1 | Name | Location | Description | Details | | --- | --- | --- | :---: | | u2_mem_ctrl | mlite_cpu.vhd#194 | | | ## Generics Count: 0 ## Ports Count: 17 | Name | Mode | Type | Description | | --- | --- | --- | --- | |clk|in|std_logic|| |reset_in|in|std_logic|| |pause_in|in|std_logic|| |nullify_op|in|std_logic|| |address_pc|in|std_logic_vector ( 31 downto 2 )|| |opcode_out|out|std_logic_vector ( 31 downto 0 )|| |address_in|in|std_logic_vector ( 31 downto 0 )|| |mem_source|in|mem_source_type|| |data_write|in|std_logic_vector ( 31 downto 0 )|| |data_read|out|std_logic_vector ( 31 downto 0 )|| |pause_out|out|std_logic|| |address_next|out|std_logic_vector ( 31 downto 2 )|| |byte_we_next|out|std_logic_vector ( 3 downto 0 )|| |address|out|std_logic_vector ( 31 downto 2 )|| |byte_we|out|std_logic_vector ( 3 downto 0 )|| |data_w|out|std_logic_vector ( 31 downto 0 )|| |data_r|in|std_logic_vector ( 31 downto 0 )||
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