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# Component - pipeline ## Summary | Name | Location | Description | | --- | --- | --- | |pipeline|mlite_pack.vhd#321|| ## Generics Count: 0 ## Ports Count: 26 | Name | Mode | Type | Description | | --- | --- | --- | --- | |clk|in|std_logic|| |reset|in|std_logic|| |a_bus|in|std_logic_vector ( 31 downto 0 )|| |a_busD|out|std_logic_vector ( 31 downto 0 )|| |b_bus|in|std_logic_vector ( 31 downto 0 )|| |b_busD|out|std_logic_vector ( 31 downto 0 )|| |alu_func|in|alu_function_type|| |alu_funcD|out|alu_function_type|| |shift_func|in|shift_function_type|| |shift_funcD|out|shift_function_type|| |mult_func|in|mult_function_type|| |mult_funcD|out|mult_function_type|| |reg_dest|in|std_logic_vector ( 31 downto 0 )|| |reg_destD|out|std_logic_vector ( 31 downto 0 )|| |rd_index|in|std_logic_vector ( 5 downto 0 )|| |rd_indexD|out|std_logic_vector ( 5 downto 0 )|| |rs_index|in|std_logic_vector ( 5 downto 0 )|| |rt_index|in|std_logic_vector ( 5 downto 0 )|| |pc_source|in|pc_source_type|| |mem_source|in|mem_source_type|| |a_source|in|a_source_type|| |b_source|in|b_source_type|| |c_source|in|c_source_type|| |c_bus|in|std_logic_vector ( 31 downto 0 )|| |pause_any|in|std_logic|| |pause_pipeline|out|std_logic||
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